Test report DSG-1056 · Rev E · tested October 15, 2026

Foundries & ManufacturingDevice under test

TSMC CEO: Profitability Has No Ceiling, High-NA EUV Coming 2030

TSMC CEO C.C. Wei says profitability has no ceiling and plans High-NA EUV lithography adoption in 2030, setting a marker for the chip industry's next capital-spending cycle.

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Spec summary

  1. TSMC CEO says the company's profitability has no ceiling.
  2. TSMC plans to adopt High-NA EUV lithography in 2030.
  3. High-NA EUV raises numerical aperture from 0.33 to 0.55 for finer chip features.
  4. TSMC is the world's largest contract chipmaker and ASML's biggest EUV customer.
TSMC CEO says profitability has no ceiling, plans High-NA EUV adoption in 2030 - digitimes
Fig. ATSMC CEO says profitability has no ceiling, plans High-NA EUV adoption in 2030 - digitimes — AI-generated

TSMC CEO C.C. Wei says the company's profitability has no ceiling, and he has put a date on the industry's next lithography leap: High-NA EUV adoption in 2030.

The remarks, reported by DigiTimes, package two messages into one statement. The first is financial. The second is technical. Together they sketch TSMC's view of the next half-decade.

Let's unpack the terminology. EUV stands for extreme ultraviolet lithography, the process that etches chip patterns with 13.5-nanometer light. High-NA EUV raises the numerical aperture (the lens system's light-gathering power) from 0.33 to 0.55, enabling finer features and, in principle, cheaper printing of the densest chip layers.

What does the 2030 date change for the industry?

Plenty. High-NA EUV tools, built solely by ASML, carry list prices reported at roughly $380 million per unit. Adopting them is a capital decision measured in billions, not millions.

A 2030 timeline means TSMC — the world's largest contract chipmaker and ASML's biggest EUV customer — sees several more years of value in current 0.33-NA tools. That's a signal to the entire supply chain: equipment makers, materials vendors, and fab-tooling planners can pace their own roadmaps against it.

It also sets a rough marker for competitors. Intel has positioned itself as an early High-NA adopter; TSMC's stated 2030 window frames how the two giants time their transitions differently.

What's behind the 'no ceiling' claim?

Wei's phrasing is blunt for a CEO. Chip-industry executives usually hedge on margins, citing capital intensity and cyclical demand. Saying profitability has "no ceiling" is a confidence statement about TSMC's pricing power and its grip on advanced nodes.

The context matters. TSMC manufactures the overwhelming majority of the world's most advanced logic chips, serving customers including Apple, NVIDIA, and AMD. Foundries at that tier face little direct competition at the leading edge.

High-NA EUV in 2030 fits that thesis. If the tools arrive on schedule, TSMC can keep pushing transistor density — and keep charging premiums for it — well into the next decade.

What we don't know yet

Wei's reported comments leave gaps. No capex figure for the High-NA rollout. No node name attached to the 2030 adoption. No word on how many tools TSMC has ordered, or from whom beyond the implied ASML relationship.

The industry will fill those gaps over the coming quarters. Watch TSMC's earnings calls and ASML's order book for the first hard numbers.

For now, the headline facts stand: a CEO declaring unlimited profitability headroom, and a firm date — 2030 — for the most expensive lithography machines ever built.

via Google News: TSMC (Source)

Filed under

  • tsmc
  • high-na-euv
  • asml
  • semiconductor-manufacturing
  • lithography
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Grace Kim

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Market editor covering regulation, policy and their impact on hardware layer of artificial intelligence at Die Signal.

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