Tensordyne's Napier inference chip runs at 300 watts against the 1,200 watts a Nvidia Blackwell B300 accelerator draws, by replacing matrix multiplication with logarithmic addition. The 138-billion-transistor device, fabricated on TSMC's 3 nm process, has taped out, co-founder RK Anand confirmed.

The startup, founded by Anand and Gilles Backhus and led since July 2022 by CEO Marc Bolitho, now counts more than 120 staff and has raised $176 million across three funding rounds. Broadcom serves as the chip shepherd for the Napier compute engine. Anand framed the supply picture bluntly: "As long as we are within lead times, we can get any volumes customers need."

What does the logarithmic trick actually do?

Multiplying matrices is hard. Adding banks of numbers is easier. Tensordyne converts activations to logarithms, adds them, and lets on-chip hardware handle the format conversion invisibly. The pitch: more than an order-of-magnitude gain in performance-per-watt and performance-per-dollar against hybrid Nvidia and AWS systems.

How is the chip built?

The Napier die integrates 138 billion transistors in TSMC N3. Each device hosts four compute banks with two columns of six logarithmic cores per bank. Tensordyne couples the cores with vector processing units and a quartet of RISC-V CPU clusters. Vector and log paths run in parallel, so post-multiply steps such as softmax overlap the matmul itself.

Napier device specifications at a glance:

• 48 logarithmic cores, each a 128×128 systolic array with a novel accumulator
• 16 RISC-V cores running at 1.5 GHz; log cores at 1.33 GHz
• 2.1 petaflops at dense FP8
• 144 GB of HBM4 across four stacks, 4.7 TB/sec aggregate bandwidth
• 256 MB on-chip SRAM, 40 TB/sec aggregate bandwidth
• NVFP4, FP8, and FP16 format support
• 300 W envelope, air cooling compatible

Gilles Backhus, vice president of AI, described the engine's three compute categories: "The main compute workhorse has 48 cores, and it has a very state of the art, very transformer architecture inspired aperture. It is 128 by 128 systolic array, basically, but with lots of extra features, such as a novel accumulator design, for example."

What does a rack look like?

A compute tray holds nine Napier chips and a 40-core Xeon host, with two 200 GbE QSFP ports and six proprietary TDNLink ports for backplane connectivity. Eight trays form a 72-chip pod, and an 8 TB NVMe flash card per tray provides local storage. A rack of four pods scales to 608 petaflops at FP8, 42 TB of HBM, 74 GB of SRAM, 266 TB of flash, and 275 TB/sec of TDNLink bandwidth. Total system draw: 120 kilowatts, air-cooled.

TDNLink uses a cell-based transport across a passive backplane, the same architectural family Nvidia's NVLink Switch uses. Backhus confirmed per-rack counts: "Per rack, we have 320 Xeon cores, and then we have another 4,608 RISC-V cores per rack."

How does throughput compare?

Tensordyne's own modeling claims a deployment of 350 Napier-based racks drives 1 billion tokens per second where a comparable Nvidia-plus-Groq or AWS-Trainium3-plus-Cerebras setup needs roughly 2,000 racks. Using equivalent datacenter footprint, the company estimates six times the token throughput at 30 percent less power.

The Napier complex sits well below the reticle limit on N3, leaving headroom for larger dies, chiplet assembly, or taller HBM stacks.

When does it ship?

Cloud access to Napier engines is targeted for late 2026. Beta TDN Pod systems reach customers in Q1 2027. Volume shipments follow in Q2 2027.