SK hynix has detailed an in-house SSD controller core, the Hynix Transaction Processing Unit (H-TPU), that draws roughly 2.5% of a general-purpose CPU core's power while occupying about 4% of its area. The company plans to deploy H-TPU clusters across its NAND portfolio, including next-generation enterprise SSD controllers, TheElec reports.

Not to be confused with an AI accelerator, an H-TPU is a small programmable core that handles routine I/O — read and write command processing, metadata management, and buffer control. Each one runs a four-stage, in-order pipeline (sequential instruction execution, no out-of-order units) suited to repetitive work. The traditional Arm CPU keeps error recovery, exception handling, and storage-policy management. It's offloading, not replacement.

Koo In-jae, SK hynix's VP of system-on-chip (SoC) design, laid out the problem at ISOCC 2026, the International SoC Design Conference, earlier this week. In a talk titled "From SSD Controllers to AI Memory SoCs," he said SSD controller CPUs are at their limit on power and area. PCIe bandwidth doubles every generation; controller CPU clocks and control capability reportedly can't keep up.

Why 'more cores' stops working

The scaling issue shows in competitor parts. Marvell's PCIe 6.0 Bravera SC6 uses 12 Cortex-R82 cores in two six-core clusters, plus three Cortex-M7 cores and a secure Cortex-M3. Its PCIe 5.0 predecessor, the Bravera SC5, listed 10 Cortex-R8 and Cortex-M7 cores plus a Cortex-M3. Core counts climb with PCIe speeds out of necessity.

Storage control requires more than 100 detailed functions — a poor fit for a monolithic CPU. SK hynix broke those functions up and spread them across "dozens of small TPU clusters," according to ZDNet Korea (translated). Each H-TPU gets a specialized job; the total exceeds 100 cores. Cluster size remains undisclosed, and neither report names the CPU core behind the 2.5% power and 4% area figures. Unused cores idle in a minimum-power mode. The design ships with a dedicated compiler and development tools for specialized code.

What does this change for controller design?

It pushes a known idea to larger scale. Phison's CoXProcessor has paired Cortex-R5 cores with hardened macros to offload repetitive firmware at wire speed for years. The Phison E18 uses two lower-clocked Cortex-R5 cores to supplement three main ones; the enterprise X1 used two Cortex-R5 cores plus up to 32 "micro cores," each dedicated to one or two tasks.

SK hynix patents describe the same split. U.S. patent 11,675,537, first filed in Korea in November 2020, details a CPU-run control plane and an I/O plane of many small processors sorted into four groups: host, cache, map, and NVM to the NAND. A command passes through all four in order, and the processors "configure a pipeline for the data I/O operation" while the CPU handles exceptions. Each small core runs about "200,000 logic gates" versus "seven million logic gates" for the CPU — roughly 2.9% of the gate count. "Firmware may be driven in each of the TPUs," making them more adaptable than hardware circuits the patent calls "difficult to modify."

Fixed hardware comes next

The next step is hardware automation (HWA): command processing, address lookup, and buffer copies moved to dedicated circuits, with the CPU and H-TPUs handling exceptions and key policy decisions. The goal is predictable completion times — essential for high-IOPS enterprise SSDs. SK hynix filed on fixed-hardware paths in 2014 and, later, in U.S. patent 12,216,914, first filed in Korea in 2022. The latter describes a "write automation circuit" and states that "a task without intelligent control can be handled or processed through the hardware layer," while firmware keeps jobs such as garbage collection.

The H-TPU reportedly appears in "Storage Next," Nvidia's name for the joint AIN P project with SK hynix, which targets 512-byte or finer NAND access. SK hynix also plans it for high-bandwidth flash (HBF), due next year. HBF stacks NAND dies for AI inference, aiming at high-bandwidth memory (HBM) bandwidth with far more capacity: up to 512GB per stack versus 64GB for HBM4. AI inference reads outnumber writes around 300,000 to 1, with the compiler and runtime passing pre-analyzed dataflow to the HBF SoC so buffer management and prefetching can hide NAND latency behind compute. In HBF stacks, a traditional multi-core Arm design is likely impractical.

No product date given. H-TPU has yet to be proven in an actual enterprise SSD controller. But the shift from general-purpose cores to single-job cores and circuits matches what SSDs actually do, and demand keeps rising as AI servers run memory-constrained — with PCIe 7.0 on the way and PCIe 8.0 headed for final ratification in 2028, simple scaling won't hold.