Nvidia is co-designing custom high bandwidth memory (HBM, stacked DRAM placed beside a processor) with Samsung and TSMC, aiming for a 30% bandwidth increase, according to a report by the Seoul Economic Daily.

The figure matters because memory bandwidth, not raw compute, now limits large AI training runs. A 30% gain would exceed what a normal generational jump in HBM delivers through standard roadmaps. The report did not specify a shipping date, a named product, or a volume target. Those omissions set the boundary of what is currently known.

What changes in the supply chain?

Until now, memory makers such as Samsung, SK Hynix and Micron designed HBM stacks to a common specification. Chip designers bought those stacks as catalog parts. Co-design moves Nvidia into the specification itself, alongside Samsung's fabrication and TSMC's packaging (the process of stacking chips and wiring them together).

For comparison: today a chipmaker picks memory the way a PC builder picks a hard drive. Under co-design, the memory is drawn into the processor's floor plan from the start, the way cache (fast on-chip memory) already is.

The report names Samsung and TSMC as partners. It does not name SK Hynix, currently the largest HBM supplier to Nvidia. Whether that absence reflects a real exclusion or incomplete sourcing is unclear. The Seoul Economic Daily did not address it.

Why does bandwidth, not capacity, drive the design?

AI accelerators move enormous tensors (multi-dimensional arrays of numbers) between memory and compute units. If memory cannot feed the units fast enough, the units idle. Vendors call this the memory wall.

A 30% bandwidth gain would let a fixed number of accelerators process larger models, or the same models faster. But the claim needs stress-testing.

• Bandwidth gains often cost power. The report gives no thermal or efficiency figures.
• Custom silicon raises cost per stack. No pricing information appears in the report.
• Yield on new stack designs is unproven at volume. No yield data was provided.

Each promise in the report carries a missing number beside it. That is normal for an early-stage disclosure. It is also a reason to treat the 30% figure as a design target, not a measured result.

Who benefits, and who is exposed?

Samsung gains the most visible benefit. The company has trailed SK Hynix in qualifying HBM3E (the current HBM generation) for Nvidia's platforms. A co-design agreement would give Samsung a locked-in position on future generations, assuming the partnership holds.

TSMC's role points to advanced packaging, where it already handles the silicon interposer (the wiring layer between processor and memory) for Nvidia's current accelerators. Deeper integration extends that franchise.

SK Hynix, if truly outside the arrangement, faces the largest risk. It supplies the majority of Nvidia's HBM today. A co-design lane that bypasses it would compress its share on future platforms. The report does not confirm its exclusion.

Memory buyers outside AI also face knock-on effects. Custom HBM consumes fabrication capacity. That tightens supply of conventional DRAM for servers and PCs, though the report offers no capacity estimates.

What was not said?

The report names no timeline, no generation of HBM, no per-stack capacity, and no financial terms. It does not say whether the custom design is exclusive to Nvidia or whether the partners can sell derivative stacks to other customers. Exclusivity determines whether this is a platform shift or a single-buyer arrangement.

It also does not specify which Nvidia product line the custom HBM serves. Data center accelerators are the obvious candidate, given the bandwidth motivation, but that is inference, not reportage.

The measured view

A 30% bandwidth target, two named manufacturing partners, and a strategic shift from catalog memory to co-designed stacks: those are the facts in the report. Everything else, including schedule, cost, power, and the position of SK Hynix, remains unstated. Readers should weight the news accordingly, and expect specification details to arrive over successive disclosures rather than in one announcement.