Microsoft's "Clea" Maia 300 accelerator delivers up to 7X the token throughput of a Maia 200 rack while improving performance per watt by 2.5X. The company disclosed the specifications at the Open Compute Project Summit 2026 this week. The chip is a "system in socket": seven dies and eight HBM4 stacks on an interposer, not a monolithic design.

What does the Maia 300 change for Azure?

The chip targets large agentic workloads. These span dozens to hundreds of models working in concert, whether as mixture-of-experts partitions or physically distinct models, and they need shared network and memory space at low latency. Microsoft rebuilt both the silicon and the network to serve that use case.

The package carries 288 GB of HBM4 memory, presumably from SK Hynix as with the Maia 200, delivering 18 TB/sec of HBM bandwidth. Aggregate SRAM bandwidth is estimated at 166.2 TB/sec, counterbalancing the HBM capacity. The package measures roughly 1,980 mm2 — 2.4X the estimated 810 mm2 of the Maia 200 — with a transistor count near 280 billion, plus or minus 10 percent.

Which process node and architecture does it use?

The Maia 300 moves to TSMC's 2-nanometer N2P process for compute, and it breaks out I/O and HBM controllers into separate chiplets, likely built on a 5-nanometer node for cost and yield reasons. There are four tile clusters, each with twelve tiles, and each core contains:

• a tile tensor unit (TTU)
• a tile vector processor (TVP)
• a tile data movement engine (TDMA)
• a tile control processor (TCP)
• shared L1 SRAM cache

The Maia 200, by comparison, had four clusters of ten tiles on TSMC's 3-nanometer N3P process, with nine of ten cores active per cluster for yield. It delivered 3.4X the floating point performance of the 2023 "Athena" Maia 100 through MXFP4 data formats, larger tensor matrices, and higher clocks.

How does the memory layout differ?

This is the sharpest architectural break. The Maia 200 shared all HBM memory across all compute tiles, and tightly coupled four XPUs into a shared NUMA board. The Maia 300 instead pairs two compute tiles with two HBM4 banks. Memory is not shared across the full socket. Routines that fit inside one memory bank run faster, which matters directly for GenAI inference. OpenAI's "Jalapeno" accelerator takes a similar tack.

How far does the cluster scale?

The ATL 2.0 Ethernet network lashes racks together into a coherency domain larger than anything announced by rivals. Microsoft moves from a 2U to a 1U form factor with next-generation liquid cooling, doubling XPUs per rack from 48 to 96 across two dozen servers. A full domain spans 128 racks and 12,288 accelerators in a single system image.

For scale: Nvidia and AMD build coherent domains of 72 or 144 GPUs, with Nvidia promising 576 to 1,152 in future multi-tier NVSwitch fabrics. Google's unshipped "Sunfish" TPU 8t tops out at 9,600 TPUs.

A Maia 300 rack burns about 167 kW. Microsoft reckons a gigawatt of Maia 300 deployments equals roughly 575,000 devices at 1.74 kW each, including the accelerator's share of host, storage, and networking.

What is the deployment picture?

Scott Guthrie, executive vice president for Cloud and AI at Microsoft, said the "multigenerational Azure Maia program has become a foundational element of Microsoft's AI infrastructure strategy" and promised "multi-gigawatt deployments" on Azure. Maia 200 chips already run inference for Copilot, and GitHub Copilot and Microsoft Foundry will shift to Maia 200 by year's end. Maia 200 will also run OpenAI models, Microsoft's own models, and open source models through Foundry.

Microsoft has not named its chip shepherd for Maia 300. Global UniChip (GUC) of Taiwan, 35 percent owned by TSMC, reportedly shepherded Maia 100, and is presumed to handle the later generations despite past rumors about Marvell and Broadcom.

The host CPU now sits inside the XPU node rather than outside the rack — presumed to be a 132-core Cobalt 200 series Arm server CPU. Rani Borkar, president of Azure Hardware Systems and Infrastructure, and Saurabh Dighe, corporate vice president of Systems Planning and Architecture, presented the technical deep dive.

The numbers behind the 7X claim break down simply: 36 percent more flops from Maia 200 to Maia 300, then a 100 percent gain from doubling XPUs per rack. The remaining multiple comes from architecture — memory capacity, bandwidth at every stage, and the dataflow that moves information through the system.