Leaked die shots of Intel's Nova Lake show a six-tile modular topology that combines Intel's 18A-P process with TSMC's N2P node, according to images circulating this week and surfaced by TweakTown.

That's two foundries, two nodes, one package. If the shots hold up, Nova Lake becomes the clearest example yet of Intel's shift toward a tile-based architecture (tiles being separately manufactured chiplets assembled on a single package) sourced across suppliers.

The leak matters for one reason: it shows process sourcing, not just design. Intel has said it would use external foundries for selected products, and 18A-P (Intel's enhanced 1.8-nanometer-class node) was expected to anchor its own compute tiles. N2P is TSMC's second-generation 2-nanometer-class process with backside power delivery refinements. Seeing both in one six-tile layout means Intel is splitting workloads across the two most advanced manufacturing lines in the industry.

What does the leak actually show?

The die shots reveal three things worth noting:

• Six tiles in total, arranged in a modular topology rather than a monolithic die
• Mixed process origins, with tiles attributed to Intel 18A-P and TSMC N2P
• A package-level design, meaning the tiles are integrated on a single substrate rather than built as one piece of silicon

Modular topology isn't new for Intel — Meteor Lake and Lunar Lake already used tile designs. Six tiles is more than either of those carried, and the dual-foundry split is the novel detail here.

What does this change for buyers?

Practically, nothing yet. Nova Lake hasn't shipped, and leaked die shots carry no launch dates, no SKU counts, no pricing. What changes is the industry picture: Intel committing to TSMC's N2P for part of a flagship client platform signals deeper dependence on external leading-edge capacity than the company's earlier, mostly in-house tile mixes. For TSMC, it's another volume commitment at the 2-nanometer class. For competitors, it raises the bar on heterogeneous packaging (combining chiplets made on different processes into one working product).

Caveats, as always with leaks

Die-shot leaks get things wrong. Attribution of individual tiles to specific nodes is difficult from imagery alone, and neither Intel nor TSMC has commented on the shots. Treat the six-tile count and the node split as unconfirmed until Intel details the architecture officially.

Intel has publicly committed to 18A for its next-generation products, and Nova Lake has been widely positioned as the 18A-family client successor in Intel's roadmap communications. The leaked shots, if genuine, add the TSMC dimension that roadmap language had left open.

We'll update as Intel responds or as corroborating leaks emerge.