At OCP, Intel disclosed specifications for two new data center product lines: the D-series GPU and Xeon rack reference designs, StreetInsider reported.

The disclosure contains no pricing, no general-availability date, and no per-chip performance targets in the materials reviewed. The D-series represents Intel's third branded discrete GPU family aimed at accelerated computing, the practice of offloading specialized workloads from general-purpose CPUs to dedicated silicon.

What is the D-series?

The D-series is a forthcoming Intel GPU line intended for data center deployments. Specific figures for memory capacity, interconnect bandwidth (chip-to-chip transfer speed), and thermal design power (TDP, the maximum heat a cooling system must dissipate) have not been published.

What is a Xeon rack reference design?

A reference design is a complete hardware specification covering power, cooling, and topology that customers can adopt directly rather than engineer from individual components. Intel has historically sold chips alone and left system integration to OEMs (original equipment manufacturers).

Caveat: Intel has not disclosed the manufacturing process node (transistor geometry in nanometers) for the D-series. Earlier Intel discrete GPUs used TSMC's N5, a 5-nanometer fabrication process at Taiwan Semiconductor Manufacturing Company. A change in foundry partner or process geometry would materially affect unit cost.

Why does this matter now?

The dual announcement places Intel alongside AMD and NVIDIA, both of which have moved toward system-level offerings bundling GPU, CPU, and networking into defined rack configurations. Intel's reference-design move is a competitive response.

The Xeon rack designs follow Intel's disaggregated architecture strategy, separating compute, memory, and storage into modular pools rather than fixed chassis. SKU numbers (stock-keeping units, individual product variants), PCIe lane counts (PCI Express data pathways for component communication), and memory channel configurations have not been released.

Concrete comparison: the combined GPU-plus-rack disclosure resembles AMD's and NVIDIA's OCP 2023 presentations, where both vendors introduced rack-scale reference designs alongside chip-level disclosures. The pattern suggests disaggregated accelerator procurement has become standard among hyperscale buyers, the largest data center operators.

What is missing from the announcement?

The disclosed materials contain no per-GPU memory capacity figures, no interconnect bandwidth numbers, and no TDP targets. Compliance with the Open Accelerator Infrastructure (OAI) specification, an OCP working group standard for modular AI system components, was referenced without elaboration.

Caveat: no executive quotation accompanied the disclosure. Intel has not yet issued a separate corporate press release on the OCP announcements.

How should buyers read OCP disclosures?

OCP announcements are pre-commercial. Products disclosed at past OCP events reached general availability twelve to eighteen months later. Specifications should be treated as preliminary engineering targets until volume shipping dates appear.

Three signals will clarify execution after this disclosure:

• MLPerf benchmark submissions (MLPerf is an industry-standard machine learning performance suite)
• Foundry partner confirmation for D-series silicon
• Hyperscaler order announcements

Caveat: OCP is a working-group forum, not a commercial launch pad. Any product cited at the summit may shift specifications, branding, or timing before volume shipment.