DeepSeek has reduced its high-bandwidth memory (HBM) cache requirements by 75% and its solid-state drive (SSD) requirements by 87.5%, according to the reported figures circulating under the Moomoo headline "DeepSeek Cut HBM Cache Needs 75% and SSD 87.5%. What Does It Mean for Memory?"

The two numbers are the story. A 75% reduction in HBM cache needs and an 87.5% cut in SSD requirements signal that at least one major AI developer can now serve large language model workloads with a fraction of the memory hardware previously considered mandatory. That has direct consequences for memory vendors, GPU and accelerator designers, and data center operators sizing their storage tiers.

What do the 75% and 87.5% figures actually measure?

The headline figures describe DeepSeek's memory footprint per unit of AI work — specifically the high-bandwidth memory used as cache on AI accelerators and the SSD capacity used for storage underneath those systems. Before these reductions, HBM was treated as the binding constraint on accelerator design, and fast NAND storage absorbed the overflow of model weights, checkpoints, and KV-cache data.

Cutting HBM cache needs by 75% means DeepSeek can run comparable workloads with one quarter of the previous HBM allocation. Cutting SSD needs by 87.5% means the storage tier shrinks to one eighth of its former size. Both cuts land on the most expensive memory products in the stack: HBM commands a large price premium over standard DRAM, and enterprise NVMe SSDs carry similar premiums over client-grade NAND.

Why does this matter for memory suppliers?

Memory makers — Samsung, SK hynix and Micron dominate the HBM segment — have priced years of AI-driven capacity growth into their capital plans. HBM in particular has been the industry's highest-margin product, sold out well in advance on the strength of accelerator demand.

A single developer's 75% reduction does not, on its own, collapse that demand curve. But if the efficiency techniques behind it generalize across the industry, every point of reduced HBM per workload compounds into a materially smaller order book. The 87.5% SSD figure points the same direction for NAND suppliers, who have counted on AI storage as their next volume market after the smartphone and PC cycles matured.

What does it mean for AI infrastructure costs?

For buyers, the arithmetic works in their favor. HBM typically accounts for a large share of an AI accelerator's bill of materials; a 75% reduction in cache requirements translates directly into fewer HBM stacks per system, lower cost per inference or training run, and less pressure on a supply chain that has been capacity-constrained.

The SSD side compounds the savings. Storage tiers in AI data centers scale with model size and data retention requirements, and an 87.5% cut shrinks that tier to a fraction of its budgeted footprint — less rack space, less power, less cooling.

Is this a demand problem or a demand shift?

The question the headline poses — "What does it mean for memory?" — cuts two ways.

The bearish reading: efficiency gains of this magnitude historically precede margin compression in the components they affect. If AI workloads need 75% less HBM cache and 87.5% less SSD capacity, the memory industry's AI growth story gets rewritten at lower unit volumes.

The bullish reading: lower cost per workload expands the total market. Cheaper memory per inference makes previously uneconomic AI applications viable, and aggregate memory demand could rise even as per-workload requirements fall — the same dynamic that has played out across every prior compute-efficiency cycle.

Which reading holds depends on elasticities the current figures alone cannot settle. What the numbers do establish is that DeepSeek has moved the efficiency frontier far enough that memory planners can no longer extrapolate from per-workload requirements set in 2023 and 2024.

What should buyers and vendors watch next?

• Adoption of the techniques beyond DeepSeek. Whether the 75% and 87.5% reductions are specific to DeepSeek's architecture or transferable across model families determines the scale of impact.
• HBM pricing and contract volumes. Forward pricing on HBM3E and successor products will reveal whether suppliers expect the cuts to spread.
• Enterprise SSD order patterns. NAND vendors' guidance will show whether the 87.5% figure is already reflected in customer forecasts.
• Accelerator roadmaps. GPU designers build products around assumed HBM capacities; a 75% cut in cache needs changes those assumptions.

The reported figures — 75% for HBM cache, 87.5% for SSD — are the hardest data points available, and they are large enough that no memory market participant can ignore them.