China's LineShine supercomputer at the National Supercomputing Center (NSC) Shenzhen has taken the number one position on the June Top500 list, delivering just under 2.2 exaflops on the High Performance Linpack (HPL) benchmark with 13,789,440 active cores across 22,680 LX2 compute nodes.

The system outperforms Lawrence Livermore's "El Capitan" — the AMD MI300A-based machine that previously held the top spot — by 21.5%. It also surpasses China's earlier exascale-class systems: the SW26010-Pro-powered "OceanLight" (1.22 petaflops HPL, 41.93 million cores) at NSC Qingdao and the Phytium 2000 plus Matrix 3000 hybrid "Tianhe-3" (1.57 exaflops HPL, 2.05 exaflops peak) at NSC Guangzhou.

What hardware powers LineShine?

The LingKun LX2 processor was designed by NSC Shenzhen in partnership with Huawei's HiSilicon chip division. Each LX2 socket combines two chiplets with 48 core blocks of four cores each — 384 raw cores per socket. That yields 304 active cores at a 79.2% yield rate.

The chip uses an Armv9.2 core with SVE2 vector units, SME matrix math units, and integer processing units.

Key LX2 specifications:

• Foundry: SMIC 7nm N+3 process
• Clock speed: 1.55 GHz
• TDP: 690 W per socket
• HBM: 16 stacks (8 per chiplet), 64 GB per socket, 8 TB/sec aggregate bandwidth
• DRAM: 256 GB LPDDR5X per socket across 8 NUMA domains

Per-socket throughput reaches 60.3 teraflops at FP64 and 120.6 teraflops at FP32 via the SME and SVE2 units. NSC Shenzhen disclosed these figures in a paper titled "Breaking the Training Barrier of Billion-Parameter Universal Machine Learning Interatomic Potentials," published April 17.

How does the system scale?

LineShine stacks compute in a four-tier hierarchy:

• Node: 2 LX2 sockets
• Blade: 8 nodes linked over PCI-Express 5.0
• Frame: 16 blades, 256 LX2 CPUs
• Cabinet: 2 frames, 30.87 petaflops FP64

The full machine comprises 184 compute frames plus 32 network frames, connected by the proprietary LingQi interconnect — analysts describe it as either an Ethernet derivative or a modified InfiniBand implementation.

LingQi uses a four-layer fat-tree topology delivering 1.6 Tb/sec per node (two 400 Gb/sec ports) and 1.07 microsecond single-hop latency. Full bisection bandwidth exceeds 3.5 Pb/sec.

The HPL configuration used 22,680 nodes — 2,200 more than the standard 20,480-node production deployment, which runs 12,451,840 cores. Peak theoretical performance of 2.74 exaflops requires 32.9% fewer cores than OceanLight needed for 46.7% more theoretical throughput.

Why does LineShine burn 42.2 MW?

The full system consumes 42.2 megawatts — substantially more than the roughly 30 MW used by Frontier, El Capitan, and Argonne's Aurora.

NSC Shenzhen deliberately throttled the LX2 to 1.55 GHz, well below SMIC's 3 GHz capability at 7nm, to hit a thermal sweet spot and compensate with core count and HBM bandwidth.

Computational efficiency on HPL reached 80.35% — below the K computer's 93% record and Fugaku's 82.3%, but achieved without GPU offload complexity. The LX2's unified HBM and DRAM memory model eliminates the software overhead that Nvidia and AMD embed in their accelerators.

What role does self-sufficiency play?

China's pursuit of compute independence, driven by US export controls on Nvidia and AMD accelerators, shapes LineShine's architecture. The LX2 substitutes domestic SMIC 7nm silicon and likely ChangXin Memory Technologies LPDDR5X DRAM for restricted alternatives.

Frontier, for comparison, reached 1.19 exaflops HPL against 1.68 exaflops peak with 8.7 million cores. The Oak Ridge machine entered service in May 2022 — more than a year after China's earlier exascale systems began running.

Yutong Lu, LineShine's main architect, presented detailed specifications at the second International Forum for HPC and AI Co-Driven Innovation (HACI 2026) in Shenzhen, May 22-25. The presentation was not released publicly.

Torsten Hoefler, chief architect for AI and machine learning at CSCS Switzerland and professor at ETH Zurich, posted slides from the event on social media. Tadashi Ogawa, technical sales manager for Panasas in Japan, did the same.

What else did the April paper disclose?

The same April 17 paper also revealed a separate exascale-class machine, the China New-generation Intelligent Supercomputer (CNIS), built on 5,632 nodes with undisclosed 64-bit CPUs and eight GPUs of unknown origin. According to the paper: "The host processor runs at 2.4 GHz with 64 cores in a NUMA architecture, connected to 8-channel DDR5-6400 memory and PCIe Gen5 interfaces, delivering 64 GB/s host-to-device bandwidth. Each GPGPU provides 32.7 TFLOPS (FP64), 65.5 TFLOPS (FP32), and 470 TFLOPS (FP16) peak performance, with 64 GB HBM (1.8 TB/sec bandwidth)."

CNIS nodes connect through a proprietary InfiniBand-like RDMA network with a three-layer Clos dual-plane topology, providing 4×400 Gb/sec per node.